1) Field of the Invention
This invention relates to a fabrication method for an electrically programmable read-only memory device, which has high efficiency of electron injection from channel to floating gate.
2) Description of the Prior Art
Side wall polysilicon gates have been used as floating gates in Flash memory. As shown in FIG. 1 the typical side wall process forms spacers on both sides of the word gate, AG. However, because most of the embedded logic applications utilize only one floating gate, FG per word gate, the unused side spacer is removed or disabled. A tunnel oxide is under the floating gate, FG and word gate, AG. Source and Drain regions are in the silicon substrate. A silicon oxide layer, SiO.sub.2 covers the gate, AG. Silicon oxide/silicon nitride/silicon oxide, ONO layers insulates the gates from one another. The control gate, CG is positioned above the device structure. Y. Yamauchi, "A 5V-only Virtual Ground Flash Cell with an Auxiliary Gate for High Density and High Speed Applications", IEDM 1991, page 319 implants N-dopants such as Arsenic or Phosphorus under the unwanted gate using a block mask, prior to formation of the side wall spacer, in order to short the unwanted gate to the adjacent diffusion. In another approach, the unwanted polysilicon gate material is used to fill the self aligned contact, as shown by Seiki Ogura U.S. Pat. No. 5,780,341.
In the U.S. Pat. No. 5,780,341 and the Patent Application of Seiki Ogura Ser. No. 09/128,585 filed Aug. 3, 1998 (HAL098-004), it is explained thata the ultra short Split Gate Flash Transistor provides high injection efficiency with low voltage and low current. Also, the fabrication technique to form controlably the ultra short channel, small as 30 nm by double sidewall technique had been shown.
However, in integrating the Split Gate Flash Transistor and high voltage devices in logic technology an optimum process which provides simplicity and reliability has not been considered enough. The logic gates, high voltage gates, and memory gates are all dimensionally critical and their relative positions are important. Therefore, it is preferable to define all three types of devices together at once rather than by separate masking processes. However, this preferred idea faces difficulty once the logic gate oxide becomes thin as 3.0 nm in the 0.18 micron feature size technology.
If the logic gates are formed prior to the side wall gates, the side wall spacers on the logic gates need to be removed, and the edges of the logic gate oxide could be damaged during the removal. On the other hand, if the logic gates are defined by a second critical mask after the memory word gates and spacer gates have been defined and formed, the damage to the logic gates' oxide during spacer removal, can be avoided. But the second approach requires two critical masks to define memory word gate and logic gate separately.